1. Field of the Invention
The invention relates to method of transferring a pattern from a patterning device onto a substrate using a lithographic apparatus, to a device manufacturing method. The invention further relates to a lithographic apparatus constructed and arranged to carry out the method, and to a computer program product for controlling a lithographic apparatus to implement steps of the method.
2. Related Art
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., comprising part of, one, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
Whichever type of apparatus is employed, the accurate placement of patterns on the substrate is a chief challenge for reducing the size of circuit components and other products that may be produced by lithography. In particular, the challenge of measuring accurately the features on a substrate which have already been laid down is a critical step in being able to position successive layers of features in superposition accurately enough to produce working devices with a high yield. So-called overlay should, in general, be achieved within a few tens of nanometers in today's sub-micron semiconductor devices, down to a few nanometers in the most critical layers.
Consequently, modern lithography apparatuses involve extensive measurement or ‘mapping’ operations prior to the step of actually exposing or otherwise patterning the substrate at a target location. These operations, being time-consuming, limit the throughput of the lithography apparatus, and consequently increase the unit cost of the semiconductor or other products. Various steps have been taken to mitigate these delays in the prior art. Nevertheless, an overhead is still incurred which limits the throughput that can be achieved.
As pattern features become smaller and overlay performance requirements become ever more demanding, so-called advanced alignment models have been and continue to be developed to model and correct more accurately non-linear distortions of the wafer ‘grid’. These advanced models depend however on measuring an increased number of targets across the wafer, which is naturally more time-consuming, and further limits the throughput of the lithographic process as a whole. For coming production nodes (for example 28 nm and below), it is believed process-induced wafer grid deformation will become a more significant contributor to overlay error. Consequently the overlay of any critical layer should ideally be controlled with advanced alignment models. At the same time, it is known that the usage of advanced alignment models increases the need for alignment information and decreases productivity, simply because more alignment marks (targets) have to be measured to secure sufficient data as input for the complex applied alignment model. The additional measurement overhead therefore threatens to reduce the throughput of processes achieving the highest overlay performance.
Additionally, when advanced alignment is used (to meet the overlay requirement), the subsequent layer has to follow this per wafer alignment induced wafer grid corrections to meet overlay specifications. This will continue for all subsequent product layers until overlay can absorb the penalty.